// จจจจจจจจจจจจจADCจจจจจจจจจจจจจจจจจจจ
void StartConv(){
    // Start Conversion for each channel

    ADC12CTL0 |= ADC12ENC + ADC12SC;
    //ADC12CTL0 &= ~(ADC12ENC + ADC12SC);

}


void adc_cfg(){
    ADC12CTL0 &= ~ADC12SC;          // nenhuma conversao
    ADC12CTL0 &= ~ADC12ENC;         // desabilita conversor
    REFCTL0 &= ~REFMSTR;            // Turn off Master Reference

    ADC12MCTL0 |= ADC12INCH_0       // Select A0 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS
    ADC12MCTL1 |= ADC12INCH_1       // Select A1 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS
    ADC12MCTL2 |= ADC12INCH_2       // Select A2 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS
    ADC12MCTL3 |= ADC12INCH_3       // Select A3 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS
    ADC12MCTL4 |= ADC12INCH_4       // Select A4 Input Channel
                + ADC12EOS          // End of sequence
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS

    ADC12MCTL5 |= ADC12INCH_5       // Select A5 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS
    ADC12MCTL6 |= ADC12INCH_6       // Select A6 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS
    ADC12MCTL7 |= ADC12INCH_7       // Select A7 Input Channel
                + ADC12SREF_1;      // V(R+) = VREF+ and V(R-) = AVSS

    ADC12IE |= ADC12IE4;

    ADC12CTL0 |= ADC12ON            // liga modulo
               + ADC12SHT0_4        // 64 CICLOS DE CLOCK DO AD para amostragem nos canais 0 a 7
               + ADC12OVIE          // Overflow-interrupt enable
               + ADC12MSC           // Enable multiples conversions
               + ADC12REFON;        // Reference generator ON

    ADC12CTL1 |= ADC12SHS_0         //
               + ADC12SHP           // (PULSE SAMPLE MODE) SAMPCON
               + ADC12CONSEQ_1      // sequencia de canais (single conversion)
               + ADC12SSEL_1        // fonte de clock = ACLK ()
               + ADC12DIV_0;

}